• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
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    • 专利摘要:
    A data reading apparatus for data transmission, for reading digital data from a digital signal series obtained by comparing the level of an incoming transmission signal obtained through a transmission path with a reference level at a detector, comprises a reference clock pulse generator for generating a reference clock pulse having a period equal to substantially 1/M of a transmission digit period of the digital signal series, a detecting circuit supplied with the digital signal series and the reference clock pulse generated by the reference clock pulse generator, for generating a level variation detection pulse in phase synchronism with level varying points corresponding to rising edges and/or falling edges of the digital signal series, a frequency dividing circuit reset by the level variation detection pulse from the detecting circuit, for generating a data reading timing clock pulse with a period substantially equal to the digit period of the digital signal series and with a phase delayed with respect to the level variation detection pulse, by frequency-dividing the reference clock pulse from the reference clock pulse generator, and a data reading circuit for obtaining a data reading output signal by latching the digital signal series by the data reading timing clock pulse obtained from the frequency dividing circuit.
    公开号:SU1301326A3
    申请号:SU823468674
    申请日:1982-07-16
    公开日:1987-03-30
    发明作者:Ямада Ясухиро
    申请人:Виктор Компани Оф Джапэн Лтд (Фирма)；
    IPC主号:
    专利说明:

    11301326
    The invention relates to automation and computing and can be used to enter information from a magnetic tape into a computer.
    5 s
    The purpose of the invention is to improve the noise immunity of the device due to the correction phase of the synchronization frequency
    Fig.1.1-9 shows the device diagrams (options) and timing diagrams.
    Figs 1-3 show the threshold element 1, the first to the third triggers 2-4, the EXCLUSIVE IL 5 element, the generator of 6 clock pulses, the frequency divider 7 by ten, the decoder 8, three inverters 9-11, And 12, a pulse counter 13, the information signal of figure 1, the input signal 14, of which IQ forms is shown in figure 2, is fed to threshold element 1. In element 1, the input signal level is compared with the reference level (dashed line in figure 2). In this section, the 5 input signal is the signal received by passing a digital signal sequence through the transmit path. As a result of the comparison of the threshold levels
    The input input 14, the data and service information outputs of the device 15 and 16.20 element 1 generates a two-digit diagram of the signals at the inputs-outputs of the digital signal shown in FIG. 2 {the elements of the device are labeled with the numbers of these elements.
    This signal is fed to the corresponding inputs of flip-flops 2 and 3. From the output of flip-flop 3, the signal is sent 25 to the information input of flip-flop 4. From the generator 6 clock pulses, the e-bar clock pulses (see Fig. 2) are fed to the corresponding clock inputs of flip-flops 3 and 4, and Figures 4 and 5 designate the first 17 and second 18 analog comparators, element OR 19, first to third D-flip-flops 20-22, element 23, 24 clock pulse generator, frequency divider 25 by sixteen, this signal arrives at the corresponding inputs of the flip-flops 2 and 3. From the output trigger 3, the signal is applied 25 to the information input of the trigger 4. From the generator 6 clock pulses, the reference clock pulses (see Fig. 2) are fed to the corresponding clock inputs of the trigger 3 and 4, to the delifter 26 (which contains the inverter 30. 7 frequency and counter 13. Reference 27 and element 28), counter 29, the clock pulses are pr-the first 30 and the second 31 inputs are the reference-. By angle pulses, the period of which the voltage of the device is informative is 1/10 of the digital period (the device's input input 32, the output is then a bit period) T 33 device data, reset input 34 and output 35 of the service information of the device. The signals at the inputs and outputs of the device elements are indicated by the sequence numbers of these elements.
    40
    Figure 6 shows the first 36 and second 37 analog comparators, the SHSh 38 element, the first to the third D-flip-flops 39-41, And 42, the additional And 43 element, 44 clock pulse generator, frequency divider 45 by sixteen, decoder 46 , the pulse counter 47, the first 48 and second 49 inputs of the device reference voltage, device information input 50, device reset input 51, device data output 52, device output 53, device synchronous input 54.
    In the circuit of the decoder 46 (Fig. 7), the inverter 55, the first 56 and the second 57 IK triggers, the counter 58, the setup input 59 of the decoder, the first 60 and the second 61 outputs of the decoder, the clock input 62 of the decoder are marked.
    input signal 14, as shown in FIG.
    Trigger 3 generates a pulse shown in Fig. 2, fixing an exponential digital signal at the time of rising edge of the input reference clock pulse, and sends a pulse to the information input of trigger 4 and to the input element EXCLUSIVE OR 5. Coordination in the rise time of pulse J5 ca at the output of trigger 3 is not the same with respect to matching the rise time of the digital signal at the output of element 1, its maximum delay is equal to approximately one period of the reference clock pulse. The trigger 4 generates at the output O the pulse shown in Fig. 2, fixing the pulse from the output of the trigger 3 at the time of the rise of the front
     This reference clock pulse sends the pulse to another input of the EXCLUSIVE OR element. Accordingly, the pulse at the output of the trigger 4 is delayed relative to the pulse signals on the time diagrams of the device shown in FIGS. 6 and 7, denoted by the serial numbers of the blocks at which they output the absence of
    The device works as follows.
    In Fig. 1, an input signal 14, whose shape is shown in Fig. 2, is applied to a threshold element 1. In element 1, the input signal level is compared with a reference level (dashed line in Fig. 2). In this case, the input signal is a signal obtained by passing a digital signal sequence through the transmit path. As a result of the comparison of the threshold levels
    element 1 generates a two-digit digital signal, shown in figure 2
    element 1 generates a two-digit digital signal, shown in figure 2
    This signal goes to the corresponding inputs of flip-flops 2 and 3. From the output of flip-flop 3, the signal goes to the information input of flip-flop 4. From the generator 6 clock pulses, the reference clock pulses (see Fig. 2) are fed to the corresponding clock inputs of flip-flops 3 and 4, frequency 7 and the counter 13. The reference clock pulses are right - angle pulses, the period of which is equal to 1/10 of the digital period (hereinafter referred to as the bit period) T
    input signal 14, as shown in FIG.
    Trigger 3 generates a pulse shown in Fig. 2, fixing an exponential digital signal at the time of rising edge of an input reference clock pulse, and sends a pulse to the information input of trigger 4 and to the input element EXCLUSIVE OR 5. Coordination in the rise time of the output pulse trigger 3 is not the same with respect to matching the rise time of the digital signal at the output of element 1, its maximum delay is approximately one period of the reference clock pulse. The trigger 4 generates at the output O the pulse shown in Fig. 2, fixing the pulse from the output of the trigger 3 at the time of the rise of the front
    This is the reference clock, and sends a pulse to another input of the EXCLUSIVE OR element. Accordingly, the pulse at the output of trigger 4 is delayed relative to the pulse at the output of trigger 3 by the delay corresponding to one period of the reference clock. As a result, the element 5 EXCLUSIVE OR produces a pulse, shown in figure 2. The width of this pulse corresponds to one period of reference clock pulses, this signal is produced at the rising front and at the falling front of the digital signal at the output of element 1. Since the pulse from the output of element 5 is ablated in the vicinity of the rising and falling edges of the digital signal from the output of element 1, This pulse is a pulse of detecting a level deviation (a pulse of detecting the front) of a digital signal from the output of element 1. A pulse of detecting a level deviation from the output of element 5 is fed to the reset input de unit 7 for its zeroing front of the rise.
    Frequency divider 7 counts the reference clock pulses and delivers the resulting output signal from outputs Q, -Q4 to decoder 8. In the interval between the ninth and tenth reference clock pulse after reset, frequency divider 7 produces a signal, the repetition period of which is equal to above the bit period T, and supplies this signal from the transfer output to the input of the counter 13 counter. The decoder 8 consists of inverters 9-11 and the I-12 element on four inputs. When the inputs Q ,, Qj, Q4 of the divider often-> gy 7 exist low levels and only at the output Q a signal is created with a high level, i.e. when divider 7 counted four reference clocks, there is a high level on all four inputs of the element 12. Therefore, the element 12 And the high-level signal shown in Fig. 2 and supplies this signal to the clock input of the trigger circuit 2 as a data read synchronization clock pulse. The phase of the data read synchronization clock pulse thus obtained corresponds to the center of the bit period of the signal at input 14 shown in FIG. With the arrival of the rising edge of the above-mentioned clock pulse of data read synchronization, on trigger 2, a digital signal from the output of threshold element 1 is applied to the information input of trigger 2, the pulse at its output shown in Fig. 2 is fed to output 15 of the device. From Comparison of signals 14 and 2 in FIG. 2, it is clear that the pulse at the output of flip-flop 2 is the read information of the input signal with
    In addition, the input signal is obtained as follows. Digital data obtained after digital pulse modulation of an analog information signal is divided into predetermined sections, and a fixed structure synchronization signal is added to the signal of each section, and the error detection signal in the code and correction signal are often added. mistakes. The input signal itself is obtained from the transmission path using a time-sequential digital signal transmission. Therefore, the rising and falling edges of the input signal are not as steep as shown in Fig. 2, due to the weakening of the high frequencies in the transmit path and for other reasons. The input signal is transmitted continuously with a clock signal, and the clock signal is extracted by a clock signal detection circuit (not shown) using a fixed structure characteristic of the clock signal. The sync signal detection signal is fed to the reset input of the counter 13 through. Cut the corresponding 1st input device.
    At the time interval when the input signal at the counter resolution input (13 is high, the counter: counts the reference clock pulses at its clock speed. At output 16, the resulting output signal is obtained. The time interval at which the input signal is at the input the resolution of counter 13 has a high level, corresponds to the interval from the ninth to the tenth reference clock pulse after zeroing the frequency divider 7. However, the phase of the reference clock pulse slightly delays due to the delay introduced by the circuit boards. The elements in frequency divider 7. Therefore, at the moment when the tenth clock reference pulse is applied to counter 13, the input signal at its input of the counting resolution is still at a high level. As a result, counter 13 counts one reference clock pulse at that moment. , the calculated value at the output of the counter 13 indicates the bit from which the read data is received on the trigger 2, i.e. how many bits after the synchronizing signal lies the bit containing the read data.
    In this embodiment of the invention, if a digital signal from the THRESHOLD element 1 shown in Fig. 3 is present, the divider 7 is frequency-S by the output signal of the element 5 shown in Fig. 3, which is synchronized in phase with the rising edges and The digital signal spacing from the output of element 1, therefore, the clock synchronization pulse of reading the data from the output of the decoder 8 (FIG. 3), obtained by decoding the output signal of the frequency divider 7, is phase corrected every time 7 Tel pulse frequency output from the EX-OR element 5
    Description of the second embodiment of the proposed device. In FIG. 4, the incoming three-digit code (sign) signal depicted in FIG. 3, with BXOjpa 32, is fed to the inverting input of the comparator 17 and to the inverting instruction the input of the comparator 18. A three-digit code signal is transmitted in accordance with a partial response system. The partial response system is one of the well-known digital transmission systems. The transmitted two-digit code signal is converted to another two-digit code signal (for example, to a non-return signal by inversion), the conversion is in progress. in accordance with the partial response system, taking into account the characteristics of the magnetic head and the magnetic recording of the medium that forms the transmitter. (the path, after which the signal records the | | on the magnetic recording medium. When playing a magnetic recording medium using a magnetic head, due to the differentiating characteristic of the magnetic head winding, weakening of the low-frequency components close to the direct current component occurs.
    0
    five
    five
    Q
    0
    five
    and the high frequency components are attenuated. As a result, the form of the reproduced signal has a signal level corresponding to a level of +1 at the time of the rise of the recorded two-digit code signal, and a signal level corresponding to -1 at the time of the decay of the recorded two-digit code signal, and a signal level O at those moments of the recorded two-digit code signal , when the interval of the period of two bits is continuously level O or 1, therefore, it has the form of a three-digit code signal. In order to create a recorded, three-digit code signal from the reproduced three-digit code signal in accordance with the partial response system, high-frequency compensation is performed in the equalizer. The reproduced signal obtained at the equalizer output is a three-digit code signal shown in FIG. The reference signs above the waveform shown in FIG. 3 indicate the recorded value of the two-digit code signal.
    The inverting input of the comparator 17 from the input 30 receives the first reference voltage, indicated by 30 in FIG. 3. The non-inverting input of the comparator 18 from the input 31 receives a second reference voltage, denoted by 30 in FIG. 3. The level of the first reference voltage is selected intermediate between the peak level of the signal corresponding to the level O of the three-digit code signal and the peak level of the signal corresponding to the level +1 of the three-digit code signal at input 32. The second reference voltage is selected with the level intermediate between the peak level of the signal corresponding to the level of the three-digit code signal, and the peak level of the signal corresponding to the level -1 of the three-digit code signal at input 32.
    Accordingly, at the comparator 17, the two-digit rectangular signal shown in FIG. 3 is. The rectangular signal at the output of element 17 has a signal level at the interval corresponding to the signal level +1 of the three-digit code signal at input 32, and has a signal level O at the intervals corresponding to the signal level m -1 and O of the input three-digit code signal / Output A comparator 18 is obtained, a two-digit rectangular signal shown in FIG. This signal has a signal level of +1 in the interval corresponding to the signal level -1 of the three-digit code signal at input 32, and has a signal level of O in the intervals corresponding to the signal levels of +1 and O of the three-digit code signal at input 32. The OR element 19 generates square signal shown on fit 5. The rectangular signal from the output of the element OR 19 is fed to the corresponding information inputs of the flip-flops 20 and 21 as level detection signals.
    The signal received at the output of Q flip-flop 21, is fed to the information input of the flip-flop 22. From the generator. 24 clock pulses to the corresponding clock inputs of the flip-flops 21 and 22 receives a reference clock signal, the period of which is 1/10 of the bit period of the three-digit code signal at input 32. The output from the Q output of the flip-flop 21 and the output from the Q-output of the flip-flop 22 arrive respectively at the And 23 element , which produces a pulse, shown in figure 5. This pulse is in phase synchronization with the rising edge of the level detection signal at the output of the element OR 19, as can be seen from Fig. 5. The impulse comes from the output of the element AND 23 to the input of the load of the frequency divider 25 as a pulse for detecting a level deviation. The phase error between the rising edge of the pulse from the output of the AND 23 element and the signal from the output of the OR 19 element is not constant, and the rising edge of the pulse lags behind the rising edge of the level detection signal by an amount of delay approximately equal to one period of reference clock pulses in the maximum case.
    The information inputs of the preset D1-D4 frequency divider 25 (where D1 is the youngest and D4 is the most significant bit) receive the appropriate level, and a low level voltage is applied to the inputs D1 and D2. Inputs D3 and D4 of frequency divider 25 are connected respectively to outputs Q and Q of flip-flop 20. Frequency divider 25 counts stadial clock pulses received from a generator of 24 clock pulses, and produces a counted output signal at outputs Q1-Q4. In addition, the output of the frequency divider 25 produces a pulse with a high level, when the calculated value is 15, and a low level with the arrival of a sixteenth reference clock pulse, i.e. this
    the pulse obtained by dividing the frequency of the reference clock pulse frequency by 16 from the original frequency. The pulse at the transfer output of the frequency divider 25 is equal to 1/16 of the bit period. )
    When the signals are output Q, Q
    and Q divider 25 frequencies equal respectively to the level of logical 1,
    and the output signal is equal to the logical level O, i.e. when the calculated value is 11, the output signal from Qj is supplied by element And 28 through inverter 27, while signals
     Q1 Qi Q + directly arrive at the element And 28. The element And 28 produces a pulse, the shape of which is shown in FIG. 5. This pulse is applied to the clock input of the trigger 20 as a data read synchronization clock pulse. Thus, trigger 20 captures the signal from the output of the element OR 19 by means of the rising edge of the pulse and produces a direct output signal at the output Q, while an inverted phase signal is produced at the output Q. The pulse shown in Fig. 5 is output from the output Q of the trigger 20 to the output 33 of the device as a signal to read information. The information read signal has a signal level of +1 with respect to the levels of +1 and -1 of the three-digit code.
    The input signal is 32 and has a level O relative to the level O of a three-digit code signal, and accordingly represents the original information.
    The counter 29 is reset by the signal received from the input 34 and counts the reference clock pulses in the interval of the existence of a signal with a high level at its resolution input. So
    As the resolution input 29 of the pulse is applied with a period equal to 1/16 of the bit period, then at output 35, the counter 29 produces a calculated value. As in the case of the above-described counter 13, the output calculated value of the counter 29 indicates the bit from which information is obtained on the trigger 20, i.e. after how many bits after the synchronizing signal lies the bit of the contents of the read information.
    From a comparison of the three-digit code information signal at input 32, shown in Fig. 5, Pos.30.31, and the signal at the output of the element OR 19, shown in Fig. 5, it can be seen that the rising edge of the signal at the output of the MJIIi 19 element occurs at moments when the signal the three-digit code information signal becomes equal +1 or -1. When the signal level of the three-digit code information signal on the bit period immediately preceding the bit period of the read signal information received from the Q terminal of the flip-flop 20 is 0, the rising edge of the output signal of the lilHi 19 element is more pronounced than in the case where the signal level of the three-digit code signal information in the immediately preceding bit period is -1 or +1, Since the pulse at the output of the AND 23 element is also created in synchronism with the signal at the output of the element 19, the impulse l the output of the AND 23 is generated with different time alignment depending on whether is O or -1 (or +1) signal level of a three-digit code of the information signal in the immediately previous bit period.
    If at the frequency divider 25 the same reset value is always assumed (a predetermined information value) and the read synchronization clock pulse of information 1-sh is generated by the calculated output signal of the frequency divider 25, then data reading by trigger 20 does not execute exactly at the center of the bit period according to the value of the bit immediately preceding the data.
    five
    To prevent this phenomenon, the output signal from the output Q of the flip-flop 20 is fed to the information pre-set input D4 of the frequency divider 25 in the previous embodiment. However, the output signal from the Q terminal of the flip-flop 20 is applied to the information input terminal of the preset D3
    About frequency divider 25. Consequently, when the level of the information acquisition signal at output 33 is low, the input Levels at inputs D1, D2 and D4 become correspondingly low, while the level at input D3 becomes high. In this case, in the frequency divider 25, the value 4 will be recorded in the presence of a pulse for detecting a level deviation by
    0 25 frequency divider. When the level of the information read signal is high, a value of 8 is recorded in the frequency divider 25, provided that a pulse exists at the output of the element 23. If the signal of the information read at the output 33 turns out to be low at the time when the output signal is generated And 23, then the information in the immediately preceding bit is O, and if the signal level of the information reading at output 33 is high, then the information in the immediately preceding data is equal to 1, which can be seen from
    FIG. five.
    I
    five
    0
    Therefore, in this version of the design, if the information in the immediately preceding bit is equal to C, when the frequency divider 25 is reset, the value 4 is written in it. Now, when the calculated value reaches 11, the clock pulse
    synchronization of reading information from the output of the decoder 26 will be created in a relatively delayed manner, as shown with, using the points p1, p4 and p7 in FIG. 5. If the information is
    immediately before the bit is equal to 1, then when the frequency divider 25 is reset, the value 8 is written in it. In this case, when the calculated value reaches the value 11,
    a clock pulse synchronizing the reading of information from the output of the decoder 26 will be created somewhat ahead of the curve, as shown in figure 5 using point p5.
    P
    The clock ip pulses of information read synchronization depicted in Fig. 5, marked with dots n2, pz p6, are created every time the frequency divider 25 has sixteen reference clocks. Therefore, in accordance with the invention, the phase of the synchronization clock of reading information from the input of the decoder 26 is corrected for each rising edge of the signal from the output of the element OR 19, thereby preventing the working reading of information due to jitter. In addition, the timing for which a clock is generated to synchronize the reading of information from the output of the decoder 26 varies according to the data in the immediately preceding bit of the signal from the output of the element. OR 19. Therefore, data can be read exactly at the center of the bit period of this signal. However, in the second version of the design in FIG. 4, on condition that the rising edge of the signal is created from the code of element 19 shown



    in FIG. 55 at time t, shown in FIG. 9, pos. 38 shifted from the initial rise time during synchronization t by time x due to noise, level fluctuations and other causes in the transmitting path, the pulse of detecting deviation at the output of the AND element 23 is also created with a shift, as indicated by the momentum y in FIG. 9. If the 2S frequency divider is reset from a phase shifted pulse detecting a level deviation, frequency divider 25 will be able to further generate phase shifted clock read pulses until the correct frequency divider 25 resets.
    In addition, in the second version of the design, preset information is recorded in the frequency divider 25 using a pulse for detecting a level deviation from the output of the AND 23 element (i.e., initial setting). In the time interval between two instants of the initial setup, a synchronization pulse for reading information from the output of the decoder 26 can be generated twice, i.e. it may happen that when creating a TacO
    1326
    12
    of the data read synchronization pulse when the calculated value is equal in frequency divider 25, frequency 11, which is shown in figure 8, position 28 using point n, the pulse for detecting level deviation from the output of element 23 will be generated when the calculated value in frequency divider 25 becomes equal to 12, which is shown in FIG. 8, and the frequency divider 25 will respectively record the value 8. In FIG. B, reference numerals above the signal indicate the calculated value in the frequency divider 25.
    In this case, the frequency divider 25 starts counting from the value 8. The calculated value 11 is obtained at the moment of time before the subsequent impulse is detected to detect the level deviation from the input of the element I 23. The result is an information read synchronization clock shown in Fig. , those. because of equality15
    0
    0
    five
    0
    five
    0
    five
    the minimum pulse interval of pulses for detecting deviations in the level of one period of bits, required for counting sixteen reference clock pulses, two clock pulses {synchronization of information reading are lost within this pulse interval
    p shown in Fig.
     6
    The occurrence of this phenomenon can be prevented by using the third variant of the device design shown in FIG. 6. In the circuit of FIG. 6, output signals from inputs Q, Q4 of frequency divider 45 are provided to decoder 46. When the value calculated by the frequency divider 45 is equal to 11, for example, the decoder 46 generates a clock synchronization pulse for reading information on the output P1, 1 represented in FIG. 9, and the output 61 of the output pulse shown in FIGS. 9 and 8. From Fig. 8, it can be seen that the pulse level at the output 61 is high in the interval during which the value calculated by frequency divider 25 can be from 2 to 10. Within the specified interval, the value calculated by frequency divider 25 can be from 2 ds a normal imp is produced ls nude.
    the occurrence of deviation by damage
    Impulse with element and 43 along with
    JO
    15
    20
    25
    13 1301326
    output 61 is fed to
    a pulse of detecting a level deviation from the output of the AND 42 element. Accordingly, the signal arriving at the input of the load of the frequency divider 45 from the AND 43 element is shown in FIG. 9. This means eliminating the pulse of detecting a deviation in the level shown in Fig. 95 created with an incorrect phase, and only the impulse of detecting a deviation in the level that you worked with the normal phase is applied to the load input of the frequency divider 45. Therefore, the above error is warned. I
    Schematic construction of the decoder 46
    7, From the frequency divider by 15 (not shown), corresponding to the frequency divider 45 by sixteen, the calculated output signals in three bits with the exception of the lower bit, respectively, are fed to the inputs A, B, C of the counter 58. Fig.7 designation n - a high level, and the designation - a low level. When a low level voltage is applied to all inputs A, B, C of the counter 58, then only a low level voltage will be output at the EUT. At the other outputs, U1-U7 will have high voltage levels. If the high level is only at the input B, the low level of voltage will be obtained only at the output U1. In this case, the other outputs of the MA and V2-V7 will have high levels, for example, i-wives. Similarly, when high levels are applied to the inputs. А, В and С of the counter 58, a low voltage level will be obtained only at the output V7, at the other outputs there will be a high level.
    The signal received from the output of U1 is fed to the input 4 of the flip-flop 57 through the inverter 55. In addition, from the output of the U7 the output signal is fed to the input of the K-flip-flop 57. The incoming to the input 62
    given to the corresponding clock inputs of the flip-flops 56 and 57. Accordingly, the output Q of the flip-flop 57 generates a pulse shown in Figs. 9 and 8, and this pulse is fed to the output 61, the signal from the transfer output of the frequency divider 45 is fed to the inputs I and K of the trigger 56 At the output of the trigger 56, the clock
    14
    a data read synchronization pulse, shown in FIG. 9, is fed to output 60.
    All of the above description was made subject to reading the information in a non-self-activated digital signal sequence. However, the proposed information reading device can be similarly applied to self-clockable digital signal sequences such as a modified frequency-modulated signal (MFM) or a phase-coded signal, obtained by performing modified frequency modulation or phase coding with a minor modification. Thus, for example, when counting information in the MFM signal, the repetition period of the reference clock pulses is chosen to be equal to 1/20 of the bit period of the MFM signal. In addition, the decoding circuit of the modified frequency-modulated signal is added to the outputs 15 (FIG. 1) or 52 (FIG. 6).
    thirty
    35
    40
    In addition, between non-self-reactive digits of signal sequences and between an arbitrary code sequence of the type of separately generated code from the M-sequences, you can get the EXCLUSIVE MI function. In this case, the proposed device can be applied to a disordered digital signal sequence in which the digital signal sequence is disorganized in order to reduce the arrival rate of continuous logic 0 or 1.
    The invention is not limited to the use of a two-digit or three-digit code when a device is transmitted to an input device, as was described in the above design variants: it can be applied to four-digit and eight-character code transmissions, the reference clock pulse of the applying, reading systems, and so on. As a rule,
    M-valued code transmission systems (M is integer) exist (M-1) types of preset values in the Divider frequency from the pulse of detecting level deviation from the pulse.
    According to the proposed device, an accurate clock read synchronization pulse can be obtained for
    6
    14
    a data read synchronization pulse, shown in FIG. 9, is fed to output 60.
    All of the above description was made subject to reading the information in a non-self-activated digital signal sequence. However, the proposed information reading device can be similarly applied to self-clockable digital signal sequences such as a modified frequency-modulated signal (MFM) or a phase-coded signal, obtained by performing modified frequency modulation or phase coding with a minor modification. Thus, for example, when counting information in the MFM signal, the repetition period of the reference clock pulses is chosen to be equal to 1/20 of the bit period of the MFM signal. In addition, the decoding circuit of the modified frequency-modulated signal is added to the outputs 15 (FIG. 1) or 52 (FIG. 6).
    each bit (or each digit) even in the case where the synchronization control is performed without detecting a synchronizing signal. The device can be used to determine the data structure in sync; its signal with an arbitrary fixed information structure. For example, if the synchronization signal consists of eight bits of information, then the read 8-bit information can be stored in a register or similar device for detecting the structure.
    权利要求:
    Claims (2)
    [1]
    1. A device for entering information from a magnetic tape, containing a threshold element, whose input is the information input of the device, the first trigger, the frequency divider by ten, the decoder, the clock generator, the output of which is connected to the counting input of the frequency divider by Ten, the bit outputs of which are connected to the inputs of the decoder, the output of which is connected to the synchronization input of the first trigger, the data input of which is connected to the output of the threshold element, and the non-inverting output is the device data output Features that, in order to increase the noise immunity of the device by correcting the phase of the synchronization frequency, the second and third triggers, the IS1 SHOCK LUSCHYE element and the pulse counter are entered into it, the output of the threshold element is connected to the data input of the second trigger, the non-inverting output of which is connected to the data input of the third trigger and to the first fy input of the EXCLUSIVE OR element, the second input of which is connected to the non-inverting output of the third trigger, the synchronization input of which and the synchronization input of the second trigger connected to the output of the clock generator and to the counting input of the pulse counter, the counting resolution input of which is connected to the overflow output of the frequency divider by ten, the reset input and the output of which are the reset input and output of the service information of the device, respectively, the output of the EXCLUSIVE OR connected to the reset input of the frequency divider by ten.
    [2]
    2. Device For inputting information from a magnetic tape, containing the first analog comparator, the inverting input of which is the first input of the reference voltage of the device, the first D-flip-flop, frequency divider by sixteen, clock generator, decoder, clock generator output the input of a sixteen frequency divider, the bit outputs of which are connected to the inputs of the decoder, the output of which is connected to the synchronous input of the first D-flip-flop, the non-inverting output of which is device data, moreover, in order to increase the device noise immunity due to phase correction of the synchronizer frequency, a second analog comparator, the OR element, the second and the third D-flip-flops, the AND element and the pulse counter, the non-inverting input of the first and the inverting input of the second analog comparators is the information input of the device, and the outputs are connected to the corresponding inputs of the lillli element, the output of which is connected to the data inputs of the first and second D-flip-flops, a non-inverting input to second analog comparator is the second input of the reference voltage of the device, the output of the second D-flip-flop is connected to the data inputs and synchronization of the third B flip-flop and the first input of the And element, the second input of which is connected to the inverting output of the third D-flip-flop, and the output is connected to the load input of the frequency divider is sixteen, the inputs of the parallel discharge bits of which are the zero bus of the device, and the inputs of the old bits are connected to the non-inverting and inverting outputs of the first D-flip-flop, the overflow output is connected to the pulse count counter input input, the reset input of which and the output are the reset input and output of the service information of the device, respectively, the count input is connected to the data input of the second D. flip-flop and the clock pulse output, the bit outputs of the frequency divider sixteen are connected to the inputs of the decoder, the output of which is connected to the synchronous input of the first D-flip-flop
    17 1
    3. A device for inputting information from a magnetic tape, containing a first analog comparator, the inverting input of which is the first input of a device reference voltage, the first D-flip-flop, a sixteen frequency divider, a clock pulse generator, a decoder, a pulse clock generator output with the counting input of the frequency divider to Sixteen, the bit outputs of which are connected to the inputs of the decoder, the first output of which is connected to the synchronous input of the first B trigger, the non-inverting output of which is output m of device data, so that, in order to interfere with the device immunity by correcting the phase of the synchronization frequency, a second analog comparator, the OR element, the second and third D-triggers AND element, and the additional AND element, pulse counter The non-inverting input of the first and the inverting input of the second analog comparators are the information input of the device, and the outputs are connected to the corresponding inputs of the OR element, the output of which is connected to the data inputs of the first and second D-flip-flop. in, a non-inverting input of a second analog comparator is BTopbjM reference voltage input device, the output of the second D-flip-flop is connected to the data input of the second D-flip-flop and the first input of the AND, the second input of which Con

    5 0 0
    18
    whose third inverter D inverter output, the output is connected to the first input of an additional element, the second input of which is connected to the second output of the decoder, and the output to the load input of the frequency divider by sixteen, the inputs of the least significant bits of the parallel bus, and the high-end inputs are connected to the non-inverting and inverting outputs of the first D-flip-flop, the overflow output is connected to the pulse counter counting enable input and to the installation
    The 5 th input of the decoder, the reset input and the output of the pulse counter are the input of the reset and the service information of the device, respectively, and the counting input is connected to the inputs of the syn- {Chronization of the second and third D-triggers, The sixteen frequency divider outputs are connected to the decoder's bit inputs, the sync input of which is the device sync input.
    A. The device according to claim 3, characterized in that the decoder contains a counter, an inverter and a first
    0 and second 1K-flip-flops, the outputs of which are the first and second outputs of the decoder, respectively, the synchronous inputs are the synchronous input of the decoder, the inputs of the counter are the bit inputs of the decoder, one output of the counter is connected to the 1-input of the second IK trigger via an inverter, the other exit - with To the entrance of the second 1K-trigger.
    five
    five
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    FIG. 7
    0123156769 S 1/1 / 21st e W 1112 13 Iff 15 O 1 Z
    23
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    61 g
    ABOUT
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    Editor N.Kishtulinets
    Compiled by I. Alekseev
    Tehred A.Krarchuk Proofreader G. Reshetnik
    Order 1164/59 Circulation 673 Subscription
    VNIIPI USSR State Committee
    for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5
    Production and printing company, Uzhgorod, Projecto st., 4
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    同族专利:
    公开号 | 公开日
    JPS5813046A|1983-01-25|
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    CA1186766A|1985-05-07|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    JP56111652A|JPS5813046A|1981-07-17|1981-07-17|Data reading circuit|
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